The dynamic operating characteristics of an integrated circuit (IC), such as switching speed characteristics and min./max. edge-to-edge timing of waveforms, are typically determined by an automatic tester. For example, the tester may be programmed to transmit a series of test waveforms to various input/output (I/O) ports of a device under test (DUT), such as an IC, and measure the resulting output levels and response times of the IC. Such testing may determine whether the IC works properly and also determine the required timing of any input signals for the proper operation of the DUT.
Since such response times of the DUT are generally on the order of a few nanoseconds (ns), the transmission lines connecting the DUT to the tester should have a minimum of delay, as will be further explained later, even though this delay is taken into account by the tester when calculating the response times. A transmission line approximately 0.5 meters in length connecting a tester to a DUT may have a delay on the order of 2.5 ns.
To avoid or limit reflections of a transmitted step voltage propagating back through the transmission line due to unmatched impedances of the DUT or tester with the transmission line, the input impedance of the DUT and the tester must ideally match the characteristic impedance (Z.sub.O) of the transmission line so that all the energy provided to the input of the DUT or tester by the transmission line is completely absorbed by the DUT or tester.
In a normal operating environment for an IC (e.g., on a circuit board), the IC ports are generally connected to other devices by transmission lines of only a few inches in length, so although reflections may exist, the reflections die out within a short period of time due to the small time delay between the ends of these short transmission lines. However, in a test setup where a DUT is connected to a tester, the transmission lines are much longer and thus the relatively long delay before any reflections die out may cause a reflected step voltage to be misinterpreted as an intentionally generated test or response signal, resulting in inaccurate test results.
Further, since many pins of an IC may be bi-directional, switching from an input mode to an output mode in only a few nanoseconds, even reflections lasting only a few round-trips of the transmission line may cause the IC, having an I/O pin which has been switched from an output mode to an input mode, to undesirably be triggered by a reflected step voltage.
This problem with reflections is especially acute as the operating frequencies of the DUT increases and the rise times of the tester and DUT waveforms fall, since reflected signals being delayed several nanoseconds due to the transmission line propagation delay will be more likely to be misinterpreted as an intentionally generated test or response signal.
Similar problems with reflections may also exist where a high speed electrical device is connected to any device, not just a tester, by a relatively long transmission line.
FIG. 1 generally illustrates a prior art connection between a DUT 10 and an automatic tester 14 via a transmission line 16. FIG. 1 shows only a single transmission line connected to a single I/O pin 18 of DUT 10 for purposes of illustrating the present problems with reflections during testing of DUT 10. In an actual test setup there would typically be one transmission line for each I/O pin of DUT 10.
It will be assumed for purposes of explaining how a reflection occurs that the output signal of DUT 10 is provided by a CMOS output buffer 20, represented by a pull-up resistor having a value R.sub.hi (actually a PMOS device) and a pull-down resistor having a resistance of R.sub.lo (actually an NMOS device). In response to a control signal by DUT 10 to CMOS buffer 20, pin 18 is switched to either power supply voltage V.sub.cc through resistor value R.sub.hi or to ground via resistor value R.sub.lo. Such switching may occur at rates up to 20 MHz or faster.
A typical transmission line 16 connecting DUT 10 to tester 14 will have a characteristic impedance (Z.sub.O) on the order of 50-100 ohms, where characteristic impedance Z.sub.O is given by the equation, EQU Z.sub.O =.sqroot.L/C (eq. 1)
where
L equals the inductance of the transmission line per unit length, and PA1 C equals the capacitance of the transmission line per unit length. PA1 V.sub.r is a reflected step equal to the voltage that the termination is driven to (V.sub.t) minus the voltage at the other end of the transmission line (V.sub.a) which gave rise to the termination voltage.
Tester 14 will be assumed for this case to incorporate a comparator 24 having an input terminal coupled to transmission line 16 for comparing the input signal from transmission line 16 to a threshold voltage V.sub.th on line 26.
The input impedance of tester 14, determined by shunt resistor 27 having a value R.sub.t, is typically set to match the Z.sub.O of the transmission line 16 so that any input signals will be completely absorbed and no reflected signals created. Since the same transmission lines are typically always used with the tester, the manufacturer of the tester may easily fix this input impedance value R.sub.1 to match the Z.sub.O of the transmission line.
Tester 14 may also include a transmitter 28 selectively coupled to transmission line 16 for supplying a test waveform to DUT 10, where pin 18 of DUT 10 would first be configured to be in an input mode instead of in an output mode as shown in FIG. 1.
The prior art also sometimes incorporates diodes, such as diodes D1 and D2 in FIG. 1, at the tester termination of transmission line 16 to prevent any termination voltages from rising significantly above a threshold voltage V.sub.x and significantly below ground voltage. However, one problem with using diodes in the configuration of FIG. 1 is that V.sub.x and V.sub.y must be carefully adjusted for each DUT 10, since each DUT 10 has different characteristics which would affect the value of V.sub.x and V.sub.y.
Although the input and output impedance of tester 14 may be preset to match the Z.sub.O of transmission line 16, DUT 10 will most likely have an input impedance well above the Z.sub.O of transmission line 16 and have an output impedance well below the Z.sub.O of transmission line 16. For example, the input impedance of MOSFET input buffers are extremely high due to the insulated gate of the MOSFET, and fast MOSFET output buffers may have output impedances as low as 5 ohms. Thus, any test signal or reflected signal being provided to a pin of DUT 10 will most likely cause another reflected signal to be sent back along transmission line 16 away from DUT 10.
If neither the total terminal impedance R.sub.t of tester 14 or the impedance of pin 18 of DUT 10 is equal to the Z.sub.O of transmission line 16, then the series of reflections back and forth across transmission line 16 will repeat until these reflections die out in an exponential manner due to the attenuation in the system. The time between the steps of these reflected waveforms returning to a same terminal is twice the delay time of transmission line 16.
For simplicity, the below discussion, providing a mathematical basis for understanding reflections on a transmission line, will ignore the effect of diodes D1 and D2 in FIG. 1 and set the R.sub.hi value of the pull-up resistor of CMOS buffer 20 in FIG. 1 to R.sub.g.
In FIG. 1, if CMOS output buffer 20 puts a positive step voltage transition on transmission line 16 by connecting transmission line 16 to V.sub.cc through resistance R.sub.g, the amplitude of the step at node A shown in FIG. 1 will be EQU V.sub.a =V.sub.cc *Z.sub.O / (Z.sub.O +R.sub.g). (eq. 2)
The step of voltage V.sub.a propagates along transmission line 16 and reaches tester 14 where it produces a voltage V.sub.t across the terminating resistor R.sub.t, where EQU V.sub.t =2*V.sub.a *R.sub.t /(Z.sub.O +R.sub.t) (eq. 3)
Since R.sub.t is typically not exactly equal to Z.sub.O, there will be a reflected step which propagates back to BUT 10 with an amplitude of EQU V.sub.r =V.sub.t -V.sub.a, (eq. 4)
where
In the condition where Z.sub.O =R.sub.t, V.sub.r is zero and the activity on the line stops with a constant voltage throughout the line until the output of DUT 10 is again switched. If Z.sub.O does not equal R.sub.t then when the reflected step V.sub.r reaches pin 18 of DUT 10 it may be completely absorbed (if R.sub.g =Z.sub.O) or a new reflection will start traveling away from DUT 10.
If neither the source or the load impedances are equal to Z.sub.O, then the series of reflections is infinite, dying out in an exponential manner, with the time between steps of these waveforms being twice the delay time of the transmission line.
To make test results most valuable to a user of the DUT, realistic loading conditions should be used when testing the DUT. For example, a single output buffer in DUT 10 may drive a number of output pins of DUT, where all of these output pins are intended to be coupled to a high impedance input of another IC, such as to an input of a CMOS device. A CMOS output device in a DUT could possibly drive a single terminated transmission line, such as transmission line 16, directly since the load provided by the single transmission line and the tester (e.g., R.sub.t) will not overload the CMOS output device. However, a CMOS output device in a DUT driving a number of outputs, and hence a number of transmission lines, generally could not be so heavily loaded and still operate as it would in a realistic environment. To ameliorate this problem, the prior art, to reduce the loading on a DUT output buffer, inserts a series resistor between the appropriate DUT pin and the transmission line leading to the tester. The tester end of the transmission line is then terminated by a shunt resistor equal to the characteristic impedance (Z.sub.O) of the transmission line, where one end of the termination resistor is coupled to a voltage about midway between ground and the power supply voltage V.sub.cc to compensate for the voltage drop across the series resistor. Thus, a number of these high impedance transmission lines may be driven by the CMOS output device without unduly loading the CMOS output device.
When the output device in the DUT now drives one or more tester inputs, the final voltage produced at the tester inputs is a good, but attenuated, representation of the DUT output voltage. In the case of a 50-ohm transmission line, the resistor placed in series with the DUT output may be 150 ohms, and the termination resistor will be 50 ohms to match the transmission line Z.sub.O. This would provide an effective 4:1 attenuation of the DUT output voltage across the termination resistor.
One disadvantage to this approach is that, when the bi-directional pin of the DUT connected to the series resistor is now controlled to be an input port, and the tester now drives this DUT pin through the series resistor, the extra impedance (150 ohms in the example given) will undesirably greatly increase the rise time of the tester drive waveform at the DUT pin due to the RC low pass filter formed by the series resistor and the input capacitance of the DUT.
Further, during a DC test of the DUT where a DC current is used to load the DUT outputs to see the effect on the output voltages and to determine the output impedance of the DUT, the range of load currents that can be applied during this test is restricted because the voltage drop across the series resistor has to be accommodated by the tester current source, and the measurement of the DUT output voltage by the tester must precisely account for this resistor voltage drop. Thus, this approach for preventing an unduly heavy load on a DUT output has numerous drawbacks which adds to the complexity of testing a device.
Still further, since each DUT type generally has output devices having a different output impedance than that found in other DUT types, the series resistor has to be adjusted to take into account these various output impedances so that the tester can take account of the precise voltage drops which occur between the tester and the DUT. This means that the interface board between the tester and the DUT must be changed for testing different IC's, even in the same basic family.
What is needed in this field is a means to terminate a transmission line coupling a DUT and a tester, wherein the same transmission line and termination means can be used for testing different IC's and wherein the termination would not unduly load any DUT output. This termination should also limit reflections from interfering with the accurate test results obtained by the tester. This termination should also not substantially increase the impedance between the tester and the DUT in a manner which would increase the rise time of any drive waveform.